The present embodiments relate to transactional execution and tracking of memory data. More specifically, the embodiments relate to tracking processor transactional read and write sets to eliminate speculative mis-predictions.
The number of central processing unit (CPU) cores on a chip and the number of CPU cores connected to a shared memory continues to grow significantly to support growing workload capacity demand. The increasing number of CPUs cooperating to process the same workloads puts a significant burden on software scalability. For example, shared queues or data-structures protected by traditional semaphores become hot spots and lead to sub-linear n-way scaling curves. Traditionally this has been countered by implementing finer-grained locking in software, and with lower latency/higher bandwidth interconnects in hardware. Implementing fine-grained locking to improve software scalability can be very complicated and error-prone, and at today's CPU frequencies, the latencies of hardware interconnects is limited by the physical dimension of the chips and systems, and by the speed of light.
Implementations of hardware Transactional Memory (TM) have been introduced, wherein a group of instructions, called a transaction, operate atomically and in isolation (sometimes called “serializability”) on a data structure in memory. The transaction is a sequence of instructions that appears as if they have all been executed without any intervening interaction with another processor. The transaction executes optimistically without obtaining a lock, but may need to abort and retry the transaction execution if an operation, of the executing transaction, on a memory location conflicts with anther operation on the same memory location, also referred to as interference. Instructions are grouped together, and transactional memory requires the tracking or memory data being used. Tracking generally occurs as a cache line granularity. Two separate sets are tracking, including a read set and a write set. The read set includes all cache lines that have been read by a current transaction. The write set includes all cache lines that have been read by the current transaction.